Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits

An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages ( V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on V TH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage ( V DD) of 0.3 V, the measured noise amplitude increases from 32% of V DD to 71% of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.