Mixed serial/parallel hardware implementation of the Berlekamp-Massey algorithm for BCH decoding in Flash controller applications

Error correction in Flash memories is often based on BCH codes and algebraic decoding that employs the Berlekamp-Massey-Algorithm (BMA) for solving the key equation. Commonly, hardware implementations of the BMA perform many Galois field multiplications in parallel. This guarantees a large throughput. Alternatively, serial implementations were proposed that require less logic but result in a much slower operation, in particular if the number of correctable errors is large. This paper presents a decoding technique that combines a serial and a parallel implementation to achieve a better trade-off between throughput and space complexity.