DocumentCode
579746
Title
Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency
Author
Rodrigues, Rance ; Annamalai, Arunachalam ; Koren, Israel ; Kundu, Sandip
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
fYear
2012
fDate
24-26 Oct. 2012
Firstpage
59
Lastpage
66
Abstract
The emergence of asymmetric multicore processors(AMPs) has elevated the problem of thread scheduling in such systems. The computing needs of a thread often vary during its execution (phases) and hence, reassigning threads to cores(thread swapping) upon detection of such a change, can significantly improve the AMP´s power efficiency. Even though identifying a change in the resource requirements of a workload is straightforward, determining the thread reassignment is a challenge. Traditional online learning schemes rely on sampling to determine the best thread to core in AMPs. However, as the number of cores in the multicore increases, the sampling overhead may be too large. In this paper, we propose a novel technique to dynamically assess the current thread to core assignment and determine whether swapping the threads between the cores will be beneficial and achieve a higher performance/Watt. This decision is based on estimating the expected performance and power of the current program phase on other cores. This estimation is done using the values of selected performance counters in the host core. By estimating the expected performance and power on each core type, informed thread scheduling decisions can be made while avoiding the overhead associated with sampling. We illustrate our approach using an 8-core high performance/low-power AMP and show the performance/Watt benefits of the proposed dynamic thread scheduling technique. We compare our proposed scheme against previously published schemes based on online learning and two schemes based on the use of an oracle, one static and the other dynamic. Our results show that significant performance/Watt gains can be achieved through informed thread scheduling decisions in AMPs.
Keywords
learning (artificial intelligence); multiprocessing systems; power aware computing; scheduling; AMP; asymmetric multicore processors; core assignment; dynamic thread scheduling technique; online learning schemes; power efficiency; scalable thread scheduling; thread reassignment; thread swapping; Benchmark testing; Correlation; Estimation; Instruction sets; Message systems; Multicore processing; Radiation detectors; Asymmetric multicore; dynamic thread scheduling; heterogeneous multicore; online thread scheduling; power efficiency;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on
Conference_Location
New York, NY
ISSN
1550-6533
Print_ISBN
978-1-4673-4790-7
Type
conf
DOI
10.1109/SBAC-PAD.2012.40
Filename
6374772
Link To Document