Compensation of loop delay in a continuous-time Delta Sigma modulator through HRZ DAC feedback

Author

Afridi, Sohaib S. ; Kamboh, Awais M. ; Gohar, N.D.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Nat. Univ. of Sci. & Technol. NUST, Islamabad, Pakistan

fYear

2012

fDate

8-9 Oct. 2012

Firstpage

1

Lastpage

4

Abstract

A Continuous-Time Delta-Sigma Modulator is presented for high resolution audio frequency applications with a sampling frequency of 6.5MHz and a signal bandwidth of 10KHz. Traditionally, such architectures suffer from the issue of `loop-delay´, which arises due to various non-idealities present in the circuit. The presented design addresses this problem by using Half-Delayed Return-to-Zero feedback signaling, as opposed to the prevalent Non-Return-to-Zero feedback signaling. The integrated circuit was designed and simulated in 250nm CMOS technology. The results show an improvement of 33.3dB in Signal-to Noise Ratio and stable loop output as compared to traditional architectures.

Keywords

CMOS integrated circuits; delta-sigma modulation; digital-analogue conversion; integrated circuit design; CMOS technology; HRZ DAC feedback; bandwidth 10 kHz; continuous-time delta sigma modulator; frequency 6.5 MHz; half-delayed return-to-zero feedback signaling; high-resolution audio frequency application; integrated circuit; loop delay compensation; loop output; signal-to-noise ratio; size 250 nm; Clocks; Delay; MATLAB; Mathematical model; Modulation; Optical signal processing; Transfer functions; Continuous-Time Delta-Sigma modulator; Feedback loop; Half-delayed Return-to-Zero; Loop delay compensation; Rectangular pulse waveforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Technologies (ICET), 2012 International Conference on

Conference_Location

Islamabad

Print_ISBN

978-1-4673-4452-4

Type

conf

DOI

10.1109/ICET.2012.6375454

Filename

6375454