An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs

The efficient design of mapping solutions for heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores. This paper proposes a SystemC simulation framework for fulfilling this task featuring (i) an automated flow for the generation of SystemC timing models for the hardware cores starting from the application source code, and, in a second step, (ii) the possibility to simulate different mapping solutions simply by changing an XML descriptor and without any interaction of the designer. The proposed framework has been then applied to a case study considering an image processing application to present the possibility to integrate it as an evaluator in design space exploration environments.