Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm2 multi-standard turbo decoder

Architecture efficiency, in terms of performance/area, of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works on application-specific instruction-set processors (ASIP) do not consider or present this key point explicitly. In this paper, we consider the challenging turbo decoding application where many recent implementations have been proposed to accommodate the related large flexibility and high throughput requirements. The paper demonstrates how the architecture efficiency of instruction-set based processors can be considerably improved by minimizing the pipeline idle time. A complete ASIP-based turbo decoder is proposed with further contributions on interleaving generators, extrinsic information exchange, and rapid reconfiguration. While supporting 3GPP LTE,WiMAX and DVB-RCS turbo codes, the proposed implementation achieves a throughput of 170Mbps with 0.644mm² @65nm CMOS technology. The proposed ASIP-based turbo decoder exhibits a high architecture efficiency of 3.12 bit/cycle/iteration/mm².