DocumentCode
580288
Title
A self-healing single core architecture using dynamically reconfigurable devices
Author
Popa, C. ; Stan, A.
fYear
2012
fDate
12-14 Oct. 2012
Firstpage
1
Lastpage
6
Abstract
The IT industry has been focusing for several years on providing to users and designers the possibility of creating software applications disregarding hardware resources. Multi-processor architectures seem to be more of interest in recent developments because of their capacity to exploit programmable parallelism at acceptable costs without posing severe software designing problems. But in any thinkable scenario, software will always be dependent on the hardware it is executing on. In another matter of speaking, hardware performances will always affect software´s ability in providing results. There is also the question if the gathered results are correct or not, if the system that provides them is fast, safe and if it is a reliable and a maintainable one. This paper proposes a scalable architecture surrounding a single core microprocessor with the purpose of increasing computational speed and reliability. For achieving this, a flexible hardware platform would be appropriate, e.g. field programmable gate arrays (FPGAs). The single core system will revolve around a Picoblaze soft-core microprocessor. By generating a series of modules with the same functionality as the executing software, an N-module redundancy system will increase systems security and reliability.
Keywords
field programmable gate arrays; microprocessor chips; multiprocessing systems; reconfigurable architectures; redundancy; FPGA; IT industry; N-module redundancy system; Picoblaze soft-core microprocessor; computational reliability; computational speed; dynamically reconfigurable device; field programmable gate arrays; flexible hardware platform; hardware performance; hardware resources; multiprocessor architecture; programmable parallelism; scalable architecture; self-healing single core architecture; single core microprocessor; software application; Computer architecture; Field programmable gate arrays; Hardware; Microprocessors; Redundancy; Software; Tunneling magnetoresistance;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory, Control and Computing (ICSTCC), 2012 16th International Conference on
Conference_Location
Sinaia
Print_ISBN
978-1-4673-4534-7
Type
conf
Filename
6379222
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