An improved design of conducted EMI suppressing in SMPS

The conducted EMI problem caused by grounding net impedance has attracted more and more attention in resent years. A model of interference system including parasitic capacitance was built. The theoretical feasibility of the measure and the mechanism of the conducted EMI caused by grounding loop were discussed. This paper proposed an improved design of conducted EMI suppressing, which can reduce the parasitic capacitance between primary and secondary winding effectively. Finally, a 100W(20V5A) SMPS was built to verify the effectiveness of this theory and the experimental results were also demonstrated.