DocumentCode :
580492
Title :
Application-specific instruction processor for extracting local binary patterns
Author :
Boutellier, Jani ; Lundbom, Ismo ; Janhunen, Janne ; Ylimäinen, Jari ; Hannuksela, Jari
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Oulu, Oulu, Finland
fYear :
2012
fDate :
23-25 Oct. 2012
Firstpage :
1
Lastpage :
8
Abstract :
Local Binary Pattern (LBP) is texture operator used in preprocessing for object detection, tracking, face recognition and fingerprint matching. Many of these applications are performed on embedded devices, which poses limitations on the implementation complexity and power consumption. As LBP features are computed pixelwise, high performance is required for real time extraction of LBP features from high resolution video. This paper presents an application-specific instruction processor for LBP extraction. The compact, yet powerful processor is capable of extracting LBP features from 1280 × 720p (30 fps) video with a reasonable 304 MHz clock rate. With a low power consumption and an area of less than 16k gates the processor is suitable for embedded devices. Experiments present resource and power consumption measured on an FPGA board, along with processor synthesis results. In terms of latency, our processor requires 17.5 × less clock cycles per LBP feature than a workstation implementation and only 2.0 × more than a hardwired ASIC.
Keywords :
application specific integrated circuits; circuit complexity; digital signal processing chips; embedded systems; face recognition; feature extraction; field programmable gate arrays; fingerprint identification; image matching; image texture; object detection; object tracking; video signal processing; FPGA board; LBP features; application-specific instruction processor; embedded devices; face recognition; fingerprint matching; hardwired ASIC; high resolution video; local binary patterns extraction; low power consumption; object detection; object tracking; power consumption; processor synthesis; texture operator; Clocks; Feature extraction; Field programmable gate arrays; Interpolation; Logic gates; Power demand; Streaming media; Digital signal processors; Feature extraction; Image texture analysis; Video signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on
Conference_Location :
Karlsruhe
Print_ISBN :
978-1-4673-2089-4
Electronic_ISBN :
978-2-9539987-4-0
Type :
conf
Filename :
6385363
Link To Document :
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