• DocumentCode
    580511
  • Title

    FPGA implementation of real-time head-shoulder detection using local binary patterns, SVM and foreground object detection

  • Author

    Kryjak, Tomasz ; Komorkiewicz, Mateusz ; Gorgon, Marek

  • Author_Institution
    AGH Univ. of Sci. & Technol., Krakow, Poland
  • fYear
    2012
  • fDate
    23-25 Oct. 2012
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Pedestrian detection is an important feature in an advanced, automated video surveillance system. Unfortunately in most situations cameras are mounted in a way that, due to perspective, walking humans are occluded by each other or stationary objects and detecting a whole silhouette is not possible. But heads and shoulders are not occluded in most cases and can be used for object classification (human or not human) or for pedestrian counting. In the article a system implemented in FPGA for head-shoulder detection is presented. It is based on Local Binary Patterns for feature extraction and Support Vector Machines for classification. To reduce the false positives rate, foreground object detection is used as an additional validation criteria. The final system was implemented in a Xilinx Virtex 6 FPGA and is able to process a video stream of resolution 640×480@60 fps in real time.
  • Keywords
    feature extraction; field programmable gate arrays; image classification; image resolution; object detection; support vector machines; video signal processing; video streaming; video surveillance; SVM; Xilinx Virtex 6 FPGA; automated video surveillance system; feature extraction; foreground object detection; image resolution; local binary patterns; object classification; pedestrian counting; pedestrian detection; realtime head-shoulder detection; support vector machines; video stream; Field programmable gate arrays; Histograms; Object detection; Standards; Streaming media; Support vector machines; Vectors; FPGA; SVM; background subtraction; head-shoulder detection; real-time video processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on
  • Conference_Location
    Karlsruhe
  • Print_ISBN
    978-1-4673-2089-4
  • Electronic_ISBN
    978-2-9539987-4-0
  • Type

    conf

  • Filename
    6385387