DocumentCode
580516
Title
GPU-based acceleration of symbol timing recovery
Author
Kim, Scott C. ; Plishker, William L. ; Bhattacharyya, Shuvra S. ; Cavallaro, J.R.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA
fYear
2012
fDate
23-25 Oct. 2012
Firstpage
1
Lastpage
8
Abstract
This paper presents a novel implementation of graphics processing unit (GPU) based symbol timing recovery using polyphase interpolators to detect symbol timing error. Symbol timing recovery is a compute intensive procedure that detects and corrects the timing error in a coherent receiver. We provide optimal sample-time timing recovery using a maximum likelihood (ML) estimator to minimize the timing error. This is an iterative and adaptive system that relies on feedback, therefore, we present an accelerated implementation design by using a GPU for timing error detection (TED), enabling fast error detection by exploiting the 2D filter structure found in the polyphase interpolator. We present this hybrid/heterogeneous CPU and GPU architecture by computing a low complexity and low noise matched filter (MF) while simultaneously performing TED. We then compare the performance of the CPU vs. GPU based timing recovery for different interpolation rates to minimize the error and improve the detection by up to a factor of 35. We further improve the process by utilizing GPU optimization and performing block processing to improve the throughput even more, all while maintaining the lowest possible sampling rate.
Keywords
digital signal processing chips; error detection; graphics processing units; interpolation; iterative methods; matched filters; maximum likelihood estimation; multiprocessing systems; radio receivers; synchronisation; 2D filter structure; GPU optimization; GPU-based acceleration; ML estimator; TED; block processing; coherent receiver; graphics processing unit-based symbol timing recovery; heterogeneous CPU-GPU architecture; iterative system; low noise MF; low noise matched filter; maximum likelihood estimator; optimal sample-time timing recovery; polyphase interpolators; sampling rate; symbol timing error detection; symbol timing recovery; timing error correction; timing error detection; Graphics processing units; Indexes; Instruction sets; Interpolation; Receivers; Signal to noise ratio; Timing; DSP accelerator; GPU; coherent receiver design; symbol timing recovery; synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on
Conference_Location
Karlsruhe
Print_ISBN
978-1-4673-2089-4
Electronic_ISBN
978-2-9539987-4-0
Type
conf
Filename
6385393
Link To Document