DocumentCode
580938
Title
Improving last level cache locality by integrating loop and data transformations
Author
Ding, Wei ; Kandemir, Mahmut
Author_Institution
Pennsylvania State Univ., University Park, PA, USA
fYear
2012
fDate
5-8 Nov. 2012
Firstpage
65
Lastpage
72
Abstract
Motivated by the observation that most existing data locality optimizations do not specifically target shared last-level caches of emerging multicores and that even multicore-specific locality-oriented techniques employ either loop or data layout optimizations but not both, in this paper we present an integrated loop and data layout optimization strategy, with the goal of improving the last-level cache performance of multicores that execute multithreaded applications. We present a detailed mathematical formulation of our locality optimization strategy and present experimental data from our current implementation. Our results, collected using 14 application programs, clearly show that the proposed integrated approach is very successful in practice, and outperforms both pure loop optimization and pure data layout optimization based alternatives. Our results also indicate that the savings achieved increase with increased core count and larger data set sizes.
Keywords
cache storage; integrated circuit layout; data layout optimizations; last level cache; loop layout optimizations; mathematical formulation; multicore-specific locality-oriented techniques; Arrays; Bipartite graph; Layout; Multicore processing; Optimization; Time factors; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Type
conf
Filename
6386590
Link To Document