A silicon-validated methodology for power delivery modeling and simulation

Power integrity has become increasingly important for the designs in 32nm or below. This paper discusses a silicon-validated methodology for microprocessor power delivery modeling and simulation. There have been many prior works focusing on power delivery analysis and optimization. However, none of them provided a comprehensive modeling methodology with post-silicon data to validate the use of the models. In this paper, we present power delivery system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32nm industrial microprocessor design. Our models are able to capture the unique impacts of on-die inductance, state dependent coupling capacitance and die-package interaction. Those impacts happen to be prominent for the designs in 32nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for power delivery analysis. The impact of power delivery noise on timing margin was accurately estimated showing a good agreement to the worst-case jitter measurements.