A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Author

Marella, Sravan K. ; Kumar, Sanjay V. ; Sapatnekar, Sachin S.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

fYear

2012

fDate

5-8 Nov. 2012

Firstpage

317

Lastpage

324

Abstract

In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

Keywords

internal stresses; piezoresistive devices; three-dimensional integrated circuits; timing circuits; transistors; 3DIC; TSV-induced thermal residual stress; biaxial nature; circuit timing variations; holistic analysis; piezoresistive effect; semianalytic formulation; thermally-induced variations; transistor mobilities; transistor parameters; Analytical models; Delay; MOS devices; Silicon; Stress; Through-silicon vias; Transistors; 3D IC; Finite Element Method; Static Timing Analysis; Through Silicon Via;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on

Conference_Location

San Jose, CA

ISSN

1092-3152

Type

conf

Filename

6386629