Title :
ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest
Author :
Jong, WoeiTzy ; Wang, Hwei-Tseng ; Hsieh, Chengta ; Khoo, Kei-Yong
Author_Institution :
Cadence Taiwan, Inc., Hsinchu, Taiwan
Abstract :
In this paper, an automatic functional Engineering Change Order (ECO) problem is proposed. The contestants need to implement programs to identify the logic difference of the old netlist and the newly synthesized netlist, which agrees with new specification. How the logic difference can be presented as patch and how we measure the patch quality is explained. The program that can find the minimal patch wins.
Keywords :
integrated circuit design; technology CAD (electronics); ICCAD-2012 CAD contest; automatic functional ECO problem; benchmark suite; engineering change order; integrated circuit design; minimal logic difference identification; patch quality measurement; Benchmark testing; Design automation; Hardware design languages; Integrated circuits; Logic gates; Manuals; Wires; ECO; P&R; Synthesis;
Conference_Titel :
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
