Accurate on-chip router area modeling with Kriging methodology

Networks-on-chips (NoCs) have emerged as an effective interconnection solution for modern MPSoCs. However, NoCs are characterized by a wide range of parameters and early performance estimations have become keys. We propose an approach to build static cost models (e.g. area) of NoC components. The modeling relies on Kriging theory, which catches the complex interactions between parameters on the basis of few low-level results. Experimental results show that the produced model has a good level of accuracy and a predictable behavior.