Title :
Challenges in post-silicon validation of high-speed I/O links
Author_Institution :
Intel Corp.
Abstract :
There are increasingly number of analog/mixed-signal circuits in microprocessors and SOCs. A significant portion of mixed-signal circuits are high-speed I/O links, including serial buses such as PCIE and parallel buses such as DDR. Post-silicon validation of I/O links is hard and time-consuming, and can be critical for making a product release qualification decision. In this paper, we try to summarize key challenges in post-silicon I/O validation. We discuss potential research directions and potential solutions to improve efficiency and quality of I/O validation.
Keywords :
elemental semiconductors; high-speed integrated circuits; microprocessor chips; mixed analogue-digital integrated circuits; silicon; system-on-chip; DDR; PCIE; SOC; Si; analog/mixed-signal circuits; high-speed I/O links; microprocessors; parallel buses; post-silicon validation; serial buses; system-on-chip; Analytical models; Correlation; Debugging; Silicon; Solid modeling; Training; Tuning;
Conference_Titel :
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
