Title :
Effect of CMOS device sizing on circuit noise performance
Author :
Noori, Hamed ; Dai, Fa Foster
Author_Institution :
Adv. Enterprise Solutions (AES), AT&T, Atlanta, GA, USA
Abstract :
An often-overlooked but important CMOS device sizing approach that significantly affects circuit noise performance has been discussed theoretically and verified by simulation. It has been demonstrated that sizing a CMOS device using maximum number of gate fingers results in as much as 9dB improvement in circuit noise figure. Furthermore, and as side benefits, parasitic capacitance, linearity, and power consumption are also improved considerably. For the purpose of simulation, Common-Gate Low-Noise Amplifier (LNA) has been utilized as the reference circuit. The simulation has been carried out using 0.12μm CMOS process.
Keywords :
circuit noise; low noise amplifiers; power consumption; reference circuits; CMOS device sizing; CMOS process; LNA; circuit noise figure; circuit noise performance; common-gate low noise amplifier; gate fingers; parasitic capacitance; power consumption; reference circuit; side benefits; Indexes; Logic gates; Performance evaluation; Radio access networks; CMOS; device sizing; interdigitated gate; linearity; multi-finger; noise; parasitic capacitance; power consumption;
Conference_Titel :
IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-2419-9
Electronic_ISBN :
1553-572X
DOI :
10.1109/IECON.2012.6389028
