DocumentCode
584271
Title
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation
Author
Varma, Prab
Author_Institution
A Subsidiary of Ansys, Inc., Apache Design, Inc., San Jose, CA, USA
fYear
2012
fDate
19-22 Nov. 2012
Firstpage
233
Lastpage
238
Abstract
An overview of test generation approaches to maximize power supply noise is provided and issues related to and research directions for generation of test vectors with representative power are discussed. In particular, to facilitate the early design and validation of the power delivery network (PDN), the need for automatic high-level test generation to create functionally representative vectors that cause worst-case power events, which stress the power grid, is described.
Keywords
automatic test pattern generation; low-power electronics; power grids; PDN validation; automatic high-level test generation; automatic test pattern generation; power delivery network; power grid; worst-case power events; Analytical models; Automatic test pattern generation; Delay; Logic gates; Power grids; Switches; Vectors; :power analysis; ATPG; power grid; test generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location
Niigata
ISSN
1081-7735
Print_ISBN
978-1-4673-4555-2
Electronic_ISBN
1081-7735
Type
conf
DOI
10.1109/ATS.2012.68
Filename
6394206
Link To Document