Implementation and Optimization of the High Performance SHA-1 Model Based on FPGA

Author

Qiong, Tang ; Jianwu, Ye

Author_Institution

Coll. of Inf. Eng., Zhejiang Univ. of Technol., Hang zhou, China

fYear

2012

fDate

11-13 Aug. 2012

Firstpage

687

Lastpage

690

Abstract

Hardware implementation is the research focus on improving the processing speed of Hash algorithm. In this paper, through the analysis of the SHA-1 algorithm, the node model of round iteration is designed based on Field programmable gate array (FPGA) and optimized by means of pipelining. Experimental results show that SHA1 algorithm model with three-input adder node achieved good performance, and the maximum throughput of the optimized model reached 138.24 Gbps. The design ideas embodied in papers has universal reference value for the hardware implementation of similar hash algorithm.

Keywords

adders; field programmable gate arrays; iterative methods; optimisation; FPGA; field programmable gate array; good performance; hardware implementation; hash algorithm; high performance SHA-1 model; maximum throughput; optimization; pipelining; round iteration; universal reference value; Algorithm design and analysis; Analytical models; Data models; Field programmable gate arrays; Load modeling; Pipelines; Throughput; FPGA; Node Model; Pipeline; SHA-1;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science & Service System (CSSS), 2012 International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4673-0721-5

Type

conf

DOI

10.1109/CSSS.2012.177

Filename

6394415