High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band

Author

Cabral, Ruben ; Sarmento, Helena

Author_Institution

INESC-ID, Lisbon, Portugal

fYear

2012

fDate

5-8 Sept. 2012

Firstpage

537

Lastpage

540

Abstract

This paper describes the high level behavioral model of a baseband processor to be implemented in FPGA devices. The final target is a reconfigurable transceiver for different technologies in the 60 GHz. For now, we implement the complete model of the AV mode of IEEE 802.15.3c. Simulations with the Matlab/Simulink model permitted to determine the adequate numerical representation at the IFFT/FFT input (OFDM Modulator/demodulator) and the number of soft bits for the Viterbi decoder that minimizes the bit error rate.

Keywords

circuit analysis computing; fast Fourier transforms; field programmable gate arrays; integrated circuit modelling; inverse transforms; millimetre wave integrated circuits; radio transceivers; AV mode; FPGA devices; IEEE 802.15.3c; IFFT-FFT; Matlab-Simulink model; Viterbi decoder; baseband processor simulation; bit error rate; frequency 60 GHz; high level behavioral model; inverse fast Fourier transforms; reconfigurable transceiver; Bit error rate; IEEE 802.15 Standards; MATLAB; Mathematical model; OFDM; Streaming media; Wireless communication; FPGA; IEEE 802.15.3c; OFDM; millimetre wave; multi-gigabit; wireless HD;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design (DSD), 2012 15th Euromicro Conference on

Conference_Location

Izmir

Print_ISBN

978-1-4673-2498-4

Type

conf

DOI

10.1109/DSD.2012.72

Filename

6395724