DocumentCode :
584744
Title :
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
Author :
Mavroidis, I. ; Mavroidis, I. ; Papaefstathiou, I. ; Lavagno, L. ; Lazarescu, M. ; de la Torre, E. ; Schafer, F.
Author_Institution :
Microprocessor & Hardware Lab., Tech. Univ. of Crete, Chania, Greece
fYear :
2012
fDate :
5-8 Sept. 2012
Firstpage :
343
Lastpage :
348
Abstract :
Using FPGAs as hardware accelerators that communicate with a central CPU is becoming a common practice in the embedded design world but there is no standard methodology and toolset to facilitate this path yet. On the other hand, languages such as CUDA and OpenCL provide standard development environments for Graphical Processing Unit (GPU) programming. FASTCUDA is a platform that provides the necessary software toolset, hardware architecture, and design methodology to efficiently adapt the CUDA approach into a new FPGA design flow. With FASTCUDA, the CUDA kernels of a CUDA-based application are partitioned into two groups with minimal user intervention: those that are compiled and executed in parallel software, and those that are synthesized and implemented in hardware. A modern low power FPGA can provide the processing power (via numerous embedded micro-CPUs) and the logic capacity for both the software and hardware implementations of the CUDA kernels. This paper describes the system requirements and the architectural decisions behind the FASTCUDA approach.
Keywords :
field programmable gate arrays; graphics processing units; hardware-software codesign; integrated circuit design; parallel architectures; public domain software; CUDA kernels; FASTCUDA; FPGA design flow; GPU programming; OpenCL; central CPU; embedded design world; embedded micro CPU; graphical processing unit programming; hardware accelerators; hardware architecture; hardware-software codesign toolset; logic capacity; minimal user intervention; open source FPGA accelerator; processing power; software toolset; Field programmable gate arrays; Graphics processing units; Hardware; Instruction sets; Kernel; Multicore processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location :
Izmir
Print_ISBN :
978-1-4673-2498-4
Type :
conf
DOI :
10.1109/DSD.2012.58
Filename :
6395725
Link To Document :
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