DocumentCode
585344
Title
Measurement and analysis of SSN and Jitter of FPGA
Author
Fujita, Haruya ; Iijima, Yo ; Sudo, Toshio
Author_Institution
Shibaura-Inst. of Technol., Tokyo, Japan
fYear
2012
fDate
17-21 Sept. 2012
Firstpage
1
Lastpage
6
Abstract
Parasitic inductance that exists in a package induces SSN (Simultaneous Switching Noise) and timing jitter. These noises cause malfunction of LSI and systems. The goal of this paper is to clarify the influence of the effective inductance of the package including mutual inductance by changing the number of simultaneously switching buffers and alternating adjacent buffers in the reverse direction each other. In this study, measured SSNs were reproduced by HSPICE simulation. The whole simulation model consisted of on-chip PDN (Power Distribution Network), package PDN and board PDN, along with I/O buffer model. The simulated SSN waveforms agreed well with the measured results.
Keywords
SPICE; buffer circuits; circuit simulation; distribution networks; field programmable gate arrays; integrated circuit measurement; integrated circuit noise; integrated circuit packaging; large scale integration; timing jitter; FPGA; HSPICE simulation; I/O buffer model; LSI; adjacent buffers; board PDN; mutual inductance; on-chip PDN; package PDN; parasitic inductance; power distribution network; simulated SSN waveforms; simulation model; simultaneous switching noise; switching buffers; timing jitter; Inductance; Noise; Power measurement; Power supplies; Switches; System-on-a-chip; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility (EMC EUROPE), 2012 International Symposium on
Conference_Location
Rome
ISSN
2325-0356
Print_ISBN
978-1-4673-0718-5
Type
conf
DOI
10.1109/EMCEurope.2012.6396872
Filename
6396872
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