Three-level hysteresis current regulation for a three phase neutral point clamped inverter

This paper presents a new hysteresis current regulation strategy for a three-phase three-level neutral point clamped (NPC) inverter. The strategy uses the zero-crossing of the fundamental component of the phase leg switched voltage to select the output voltage level, with only one hysteresis comparator required per phase leg. The same average voltage is then used to vary the hysteresis band as the load back-emf changes in order to maintain a constant switching frequency. Next, the strategy is extended to a three-phase NPC inverter by subtracting the common mode interacting current from the total phase leg current error before making any switching decision. The three-phase leg current errors are also synchronized to a fixed clock frequency to further improve the frequency regulation and obtain a line to line harmonic performance that is close to open-loop phase disposition (PD) pulse width modulation.