DocumentCode :
585688
Title :
Ternary SRAM for low power applications
Author :
Jayashree, H.V. ; Sai Shruthi, V.P.
Author_Institution :
PES Inst. of Technol., Bangalore, India
fYear :
2012
fDate :
19-20 Oct. 2012
Firstpage :
1
Lastpage :
6
Abstract :
Design and Performance verification of Ternary CMOS SRAM is presented in this paper. Ternary SRAM is designed in 180nm, 90nm & 65nm technology process. The Ternary SRAM cell consists of two cross coupled Ternary inverters. READ and WRITE operations of the Ternary SRAM cell are performed with the help of Sense Amplifier, Tritline Conditioning circuits and Fast Decoders using TSPICE. The proposed work can be used for Low Power Application as the Fast Decoders use less number of Transistors compared to the conventional Decoders. The Ternary SRAM array module (1X1) in 65 nm technology consumes only 0.608mW power and data access time is about 9.88ns.
Keywords :
CMOS memory circuits; SPICE; SRAM chips; amplifiers; invertors; low-power electronics; TSPICE; cross coupled ternary inverters; fast decoders; low power applications; sense amplifier; ternary CMOS SRAM; tritline conditioning circuits; Arrays; Decoding; Inverters; Logic gates; Transistors; Power optimization; Ternary Fast Decoders; Ternary Logic; Ternary SRAM; Ternary inverter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication, Information & Computing Technology (ICCICT), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4577-2077-2
Type :
conf
DOI :
10.1109/ICCICT.2012.6398121
Filename :
6398121
Link To Document :
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