DocumentCode
585792
Title
Memristor in neuromorphic computing
Author
Hai Li
Author_Institution
Electr. & Comput. Eng., Polytech. Inst. of New York Univ., Brooklyn, OH, USA
fYear
2012
fDate
12-14 Sept. 2012
Firstpage
294
Lastpage
294
Abstract
Summary form only given. As technology scaling down becomes more and more difficult, the traditional von Neumann computer architecture cannot satisfy people´s unlimited demand on high performance computation. Consequently, the neuromorphic hardware systems providing the capabilities of biological perception and information processing at compact and energy-efficient platform have drawn people´s attention. Realizing neural network algorithms requires a large volume of memory and being adaptive to environment, which results in high design complexity and hardware cost. Not mentioning its promising characteristics, such as non-volatility, low-power consumption, high integration density, and excellent scalability, the recently rediscovered memristor device also has the unique property to record the historical profile of the excitations on the device, making it an ideal candidate to realize the synapse behavior in electronic neural networks. In this tutorial, I will introduce the utilizations of memristors in dynamic reconfigurable systems and in hardware realization of neuromorphic algorithms. The memristor-based neuromorphic system can offer extremely high computation parallelism, high resilience to process variations and transient run-time errors, and high power efficiency with ultra-low hardware cost and small footprint. Moreover, our design is fully compatible to the present-day CMOS fabrication process, demonstrating an excellent scalability.
Keywords
computer architecture; electronic engineering computing; neural nets; power aware computing; CMOS fabrication process; Memristor; biological perception; dynamic reconfigurable systems; electronic neural networks; energy efficient platform; hardware realization; high performance computation; information processing; neuromorphic computing; neuromorphic hardware systems; power consumption; von Neumann computer architecture; Awards activities; Computer architecture; Educational institutions; Hardware; Memristors; Neural networks; Neuromorphics;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2012 IEEE International
Conference_Location
Niagara Falls, NY
ISSN
2164-1676
Print_ISBN
978-1-4673-1294-3
Type
conf
DOI
10.1109/SOCC.2012.6398367
Filename
6398367
Link To Document