Variation-and-aging aware low power embedded SRAM for multimedia applications

Author

Gong, Na ; Jiang, Shixiong ; Challapalli, Anoosha ; Panesar, Manpinder ; Sridhar, Ramalingam

Author_Institution

SUNY - Univ. at Buffalo, Buffalo, NY, USA

fYear

2012

fDate

12-14 Sept. 2012

Firstpage

21

Lastpage

26

Abstract

This paper presents a low power embedded SRAM memory design for MPEG-4 video processors. Considering both of the process variation and aging effect, the proposed design adopts an optimal high voltage for spatial voltage scaling to achieve high power efficiency. Simulations in FreePDK 45nm CMOS technology show that our proposed technique can achieve 85%, 90%, and 79% reduction in write power, read power, and leakage current, respectively, with graceful degradation (~5.6%) in video quality, as compared to conventional SRAM design.

Keywords

CMOS integrated circuits; SRAM chips; digital signal processing chips; integrated circuit design; low-power electronics; multimedia computing; power aware computing; video coding; FreePDK CMOS technology; MPEG-4 video processor; embedded SRAM memory design; multimedia application; size 45 nm; spatial voltage scaling; variation-and-aging awareness; video quality; Aging; Decoding; Degradation; PSNR; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2012 IEEE International

Conference_Location

Niagara Falls, NY

ISSN

2164-1676

Print_ISBN

978-1-4673-1294-3

Type

conf

DOI

10.1109/SOCC.2012.6398371

Filename

6398371