DocumentCode :
585801
Title :
Gray-level image recognition on a dynamically reconfigurable vision architecture
Author :
Kamikubo, Yuki ; Watanabe, Minonu ; Kawahito, Shoji
Author_Institution :
Electnical and Electnonic Engineening, Shizuoka Univensity, 3-5-1 Johoku, Hamamatsu, Shizuoka 432-8561, Japan
fYear :
2012
fDate :
12-14 Sept. 2012
Firstpage :
61
Lastpage :
65
Abstract :
Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such system requires many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Realizing such high-speed real-time image recognition operation is difficflt because of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigurable vision architecture that can recognize binarized images has been presented. However, to date, no dynamically reconfigurable vision architecture that can recognize gray-level images has ever been presented. Therefore, this paper presents experimentation related to a more advanced dynamically reconfigurable vision architecture that can recognize gray-level images.
Keywords :
Dynamically reconfigfrable devices; Field Programmable Gate Arrays; Vision chips;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY, USA
ISSN :
2164-1676
Print_ISBN :
978-1-4673-1294-3
Type :
conf
DOI :
10.1109/SOCC.2012.6398381
Filename :
6398381
Link To Document :
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