Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement

Emerging hybrid-CMOS nanoscale devices and architectures offer greater degree of integration and performance capabilities. However, the high power densities, hard error/soft error frequency, process variations, and device wearout affect the overall system reliability. Reactive design techniques, such as redundancy, account for component failures by detecting and correcting the system failures. These techniques incur high area and power overhead. Our research focuses on enhancing the system reliability in hybrid CMOS/Resistive RAM (RRAM) architectures by performing computation in RRAM, whenever the CMOS logic units fail. In particular, we propose dynamically reconfiguring the RRAM cache by mapping the failed CMOS units as look up table (LUT) logic blocks in the RRAM. The proposed approach is validated on a 45nm single core processor with three levels of cache for various SPEC2006 benchmarks. Our results demonstrate that the core is fully functional when failed units are reconfigured in RRAM. Performance degradation of up to one order of magnitude and energy increase of up to two orders of magnitude is observed.