Reconfigurable framework for high-bandwidth stream-oriented data processing

Field Programmable Gate Arrays (FPGAs) have become a competitive alternative to ASICs in both cost and flexibility. This paper presents a method for migrating an existing ASIC core into an FPGA. To minimize timing effects from logic overhead in FPGAs, a reconfigurable multichannel framework is developed that achieves comparable computational performance to the original ASIC. Run-time reconfiguration is overlapped with processing, allowing for a greater application diversity. Implementations using a color space conversion engine (CSC) show that performance can be improved up to 1.5 times faster than the original ASIC design, as a result of exploiting parallelism.