Power-aware topology generation for application specific NoC design

Network-on-Chip (NoC) is a new alternative approach to bus-based and point-to-point communication methods to design large System on Chip (SoC) architectures. Designing a power-aware irregular topology for a NoC based application is a challenging problem due to its high complexity. This paper tackles at this problem and presents a genetic algorithm based topology generation algorithm (GATGA) for NoC architectures aiming to minimize the power consumed by the communication among tasks of the application. Our experiments on multimedia benchmarks and randomly generated graphs show that the proposed algorithm achieves considerable improvements over the existing topology generation algorithms in terms of communication overhead and power consumption.