Latency impacts of different parallelism levels in data-flow architectures

In this paper, different architectures of parallelized data processing subsystems are described and analysed in terms of their contribution to the overall system latency. The focus is on a comparison between bit-level and block-level parallelism in a data-flow environment. The latency influence of block-level parallelism is especially studied for algorithms with data dependencies between non-adjacent blocks. It is found that the block-level parallelism has a significant contribution to the overall system latency. Contrary to block-level parallelism, bit-level parallelism allows further latency reduction by using the “implicit interleaving” method, avoiding the necessity for a dedicated (de-) inter-leaver. Simulation results for the implicit interleaving are shown based on a 60 GHz OFDM communication system. They indicate that the implicit interleaving can be used to decrease the system latency without sacrificing error correction capabilities.