A next generation digital signal processor for European space missions

Future European space missions are in critical need of a new digital signal processor (DSP) free of any International Traffic in Arms Regulations (ITAR) restrictions. We present a new, highly parallel, 8-slot Very Long Instruction Word (VLIW) DSP modeled in LISA, a high-level architecture description language. Necessary software development tools as well as a synthesizable hardware model are generated from this abstract model automatically, improving the productivity and stability significantly. To our best knowledge, it is the first processor aimed to be used in space modeled at a higher abstraction level than RTL. The synthesis of the generated VHDL code using a 180nm CMOS standard cell library results in an area of 380 kGates and shows an aggregated peak performance of 1.0 GOPS and 750 MFLOPS, outperforming the only available other option, Atmel´s TSC21020F processor, by an order of magnitude.