Layout constrained body-biasing for thermal clock-skew compensation

In this work we investigate on the actual capability of adaptive body bias to be applied on Clock Distribution Networks (CDNs) for dynamic compensation of thermally-induced skews. Selectively applying different bulk polarizations to the clock buffers, i.e., Forward Body Bias (FBB) to speed-up, or Reverse Body Bias (RBB) to slow down, it is possible to recover the timing phase shifts which accumulate along the clock tree paths due to on-chip thermal gradients. However, the physical implementation of such technique is not trivial: While a fine tuning of the clock buffers would require to apply a cell-by-cell biasing, design constraints due to semi-custom layout rules impose a higher granularity, that is, a physical cluster of cells, i.e., a layout row. We therefore propose a row-based ILP formulation that considers the aforementioned physical constraints and that provides optimal body bias assignment for thermal clock skew minimization. As will shown for a set of realistic benchmarks mapped into an industrial 40nm technology, our solution allows real skew compensation under different thermal profiles while avoiding unfeasible conditions where buffers placed in the same row require different bulk polarizations.