Nano-power tunable bump circuit using wide-input-range pseudo-differential transconductor

An ultra-low-power tunable bump circuit is presented. It incorporates a novel wide-input-range tunable pseudo-differential transconductor linearised using the drain resistances of saturated transistors. Measurement results show that the transconductor has a 5 V differential input range with <;20% of linearity error. The bump circuit demonstrates tunability of the centre, width and height, consuming 18.9 nW power from a 3 V supply, occupying 988 μm² in a 0.13 μm CMOS process.