Integrated optimization of semiconductor manufacturing: A machine learning approach

As semiconductor process nodes continue to shrink, the cost and complexity of manufacturing has dramatically risen. This manufacturing process also generates an immense amount of data, from raw silicon to final packaged product. The centralized collection of this data in industry information warehouses presents a promising and heretofore untapped opportunity for integrated analysis. With a machine learning-based methodology, latent correlations in the joint process-test space could be identified, enabling dramatic cost reductions throughout the manufacturing process. To realize such a solution, this work addresses three distinct problems within semiconductor manufacturing: (1) Reduce test cost for analog and RF devices, as testing can account for up to 50% of the overall production cost of an IC; (2) Develop algorithms for post-production performance calibration, enabling higher yields and optimal power-performance; and, (3) Develop algorithms for spatial modeling of sparsely sampled wafer test parameters. Herein these problems are addressed via the introduction of a model-view-controller (MVC) architecture, designed to support the application of machine learning methods to problems in semiconductor manufacturing. Results are demonstrated on a variety of semiconductor manufacturing data from TI and IBM.