• DocumentCode
    586865
  • Title

    On pinpoint capture power management in at-speed scan test generation

  • Author

    Wen, Xuefeng ; Nishida, Yoshiharu ; Miyase, Kohei ; Kajihara, Seiji ; Girard, P. ; Tehranipoor, Mohammad ; Wang, L.-T.

  • Author_Institution
    Kyushu Inst. of Technol., Iizuka, Japan
  • fYear
    2012
  • fDate
    5-8 Nov. 2012
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional switching activity), or cold (with excessively-low switching activity). Then, X-restoration/X-filling-based rescue is conducted on the test vector to reduce switching activity around hot paths. If the rescue is insufficient to turn a hot path into a warm path, mask is then conducted on expected test response data to instruct the tester to ignore the potentially-false test response value from the hot path, thus achieving guaranteed capture power safety. Finally, X-restoration/X-filling-based warm-up is conducted on the test vector to increase switching activity around cold paths for improving their small-delay test capability. This novel approach of pinpoint capture power management has significant advantages over the conventionalapproachofglobalcapturepower management, as demonstrated by evaluation results on large ITC´99 benchmark circuits and detailed path delay analysis.
  • Keywords
    automatic test pattern generation; boundary scan testing; power supply circuits; X-filling-based rescue; X-restoration-based rescue; at-speed scan test generation; benchmark circuits; detailed path delay analysis; expected test response data; guaranteed capture power safety; hot paths; minimal test cost impact; pinpoint capture power management; potentially-false test response value; small-delay test capability; switching activity; test vector; warm path; Clocks; Delay; Safety; Switches; Testing; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference (ITC), 2012 IEEE International
  • Conference_Location
    Anaheim, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4673-1594-4
  • Type

    conf

  • DOI
    10.1109/TEST.2012.6401548
  • Filename
    6401548