Benchmarking ISA reliability to intermittent errors

Silicon scaling has led to accelerated wearout, which results in increased number of intermittent errors. Of the various factors that can lead to intermittent errors, device utilization is a major contributor to wearout. Every device on a chip is activated in response to either control signals or data movement resulting from instruction execution. This research proposes a systematic methodology for benchmarking the vulnerability of instruction set architecture (ISA) toward intermittent errors. By following each instruction during its execution through the processor pipeline, we quantify how many devices each instruction activates during its execution. We propose Vulnerability to Intermittent Failures (VIF) as a metric to quantify the stress imposed on circuits by an instruction. We show how VIF varies from instruction to instruction and how different inputs can affect VIF.