Title :
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS
Author :
Tuan-Vu Cao ; Aunet, Snorre ; Ytterdal, Trond
Author_Institution :
Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
Abstract :
In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency. At a sample rate of 50MS/s and a supply voltage of 1V, the 9-bit SAR ADC achieves an ENOB of 8.84 bit and consumes 45 μW, resulting in an energy efficiency of 2.01 fJ/conversion-step. The circuits are designed and simulated with parasitic models using a commercially available 28nm bulk CMOS process.
Keywords :
CMOS logic circuits; analogue-digital conversion; approximation theory; capacitors; comparators (circuits); microcontrollers; switches; asynchronous SAR ADC; bit rate 50 Mbit/s; body effect reduction; bootstrapped sampling switches; bulk CMOS process; capacitance 1 fF; charge redistribution differential DAC; digital SAR control logic; dynamic two-stage comparator; metal-metal capacitor unit; monotonic capacitor switching procedure; parasitic models; power 45 muW; size 28 nm; successive approximation register ADC architecture; voltage 1 V; word length 8.84 bit; word length 9 bit; CMOS integrated circuits; Capacitors; Logic gates; Noise; Power demand; Switches; Transistors;
Conference_Titel :
NORCHIP, 2012
Conference_Location :
Cpenhagen
Print_ISBN :
978-1-4673-2221-8
Electronic_ISBN :
978-1-4673-2222-5
DOI :
10.1109/NORCHP.2012.6403105
