A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter

In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, and pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology.