Behavioral modeling of nonlinear settling for multiple cascaded SC stages

This paper presents an efficient method to model the settling transient response of cascaded switched capacitor stages. A sigma-delta modulator was designed using non-delaying integrators to study the settling error in cascaded stages. First, a settling error look-up table model was built by separate continuous-time simulations, and then this error model was used in a fast discrete-time Simulink model. The modeling methodology is described, and the results are compared against Verilog-A simulations.