Behavioral modeling of nonlinear settling for multiple cascaded SC stages

Author

Jia Sun ; Rahkonen, Timo ; Neitola, Marko

Author_Institution

Dept. of Electr. & Inf. Eng. & Infotech Oulu, Univ. of Oulu, Oulu, Finland

fYear

2012

fDate

12-13 Nov. 2012

Firstpage

1

Lastpage

6

Abstract

This paper presents an efficient method to model the settling transient response of cascaded switched capacitor stages. A sigma-delta modulator was designed using non-delaying integrators to study the settling error in cascaded stages. First, a settling error look-up table model was built by separate continuous-time simulations, and then this error model was used in a fast discrete-time Simulink model. The modeling methodology is described, and the results are compared against Verilog-A simulations.

Keywords

sigma-delta modulation; switched capacitor networks; table lookup; Verilog-A simulations; cascaded switched capacitor stages; continuous-time simulations; discrete-time Simulink model; multiple cascaded SC stages; nondelaying integrators; nonlinear settling behavioral modeling; settling error look-up table model; settling transient response; sigma-delta modulator; Capacitors; Hardware design languages; Integrated circuit modeling; Mathematical model; Polynomials; Software packages; Table lookup; behavioral modeling; cascaded switched capacitor stages; look-up table; nonlinear settling; polynomial fitting; sigma-delta modulator;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2012

Conference_Location

Cpenhagen

Print_ISBN

978-1-4673-2221-8

Electronic_ISBN

978-1-4673-2222-5

Type

conf

DOI

10.1109/NORCHP.2012.6403136

Filename

6403136