• DocumentCode
    587725
  • Title

    Integration of TTA processor tools to Kactus2 IP-XACT design flow

  • Author

    Matilainen, Lauri ; Lahti, S. ; Esko, Otto ; Salminen, Erno ; Hamalainen, Timo D.

  • Author_Institution
    Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland
  • fYear
    2012
  • fDate
    12-13 Nov. 2012
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper presents a new freely available, open source design flow to accelerate the usage of application-specific processors in System-on-Chip designs. The proposed flow combines our Transport-Triggered Architecture (TTA) processor toolset and Kactus2 IP-XACT design environment. The IP-XACT standard and our Kactus2 tool make it easy to integrate and configure intellectual property (IP) components from multiple vendors whereas the configurable TTA provides a fast and efficient path from C-to-VHDL. We present 3 use cases for TTA: as a ready-made fixed accelerator, a general-purpose processor, and a tailored application-specific processor. Moreover, management of instance-specific data in IP-XACT is discussed. The combined design flow is presented in detail step-by-step, and the user time spent on each step is evaluated. Provided that C source codes and IP-XACT library are available, a non-HW oriented engineer can implement an FPGA based multiprocessor product in less than 5 hours.
  • Keywords
    field programmable gate arrays; hardware description languages; integrated circuit design; system-on-chip; C source codes; C-to-VHDL; FPGA; IP-XACT library; IP-XACT standard; Kactus2 IP-XACT design flow; TTA processor tools; general-purpose processor; intellectual property components; multiple vendors; nonHW oriented engineer; open source design flow; ready-made fixed accelerator; system-on-chip designs; tailored application-specific processor; transport-triggered architecture processor toolset; Field programmable gate arrays; Generators; Hardware; IP networks; Libraries; System analysis and design; System-on-a-chip; C to VHDL; IP-XACT; Kactus2; SoC; TCE; TTA;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    NORCHIP, 2012
  • Conference_Location
    Cpenhagen
  • Print_ISBN
    978-1-4673-2221-8
  • Electronic_ISBN
    978-1-4673-2222-5
  • Type

    conf

  • DOI
    10.1109/NORCHP.2012.6403151
  • Filename
    6403151