A low power 32-bit quaternary-tree adder

Author

Raad, N. ; Mansour, Mohamed M.

Author_Institution

Electr. & Comput. Eng. Dept., American Univ. of Beirut, Beirut, Lebanon

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

1

Lastpage

2

Abstract

In this paper, we implement a 32-bit quaternary tree adder and simulate the design using HSPICE in 90-nm static CMOS logic. Simulation results show that the adder can operate at 3.4 GHz (measured at 1.8V, 25°C) and dissipates 8.9 mW of power. The sparse-tree architecture achieves low carry-merge fan-outs and inter-stage wiring complexity. Compared to other designs in the literature, the quaternary tree adder has fewer carry-merge blocks and faster carry generation after removing the sum generation from the critical path.

Keywords

CMOS logic circuits; adders; HSPICE; carry generation; carry-merge fan-outs; critical path; frequency 3.4 GHz; interstage wiring complexity; low power quaternary-tree adder; power 8.9 mW; size 90 nm; sparse-tree architecture; static CMOS logic; sum generation; temperature 25 degC; voltage 1.8 V; Adders; CMOS integrated circuits; Computer architecture; Computers; Energy efficiency; Generators; Multiplexing; ALU; component; low-power; quaternary adders; tree adders;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Aware Computing (ICEAC), 2011 International Conference on

Conference_Location

Istanbul

Print_ISBN

978-1-4673-0466-5

Electronic_ISBN

978-1-4673-0464-1

Type

conf

DOI

10.1109/ICEAC.2011.6403627

Filename

6403627