Performance analysis and optimization for silicon interposer with Through Silicon Via (TSV)

In this paper, the stacked silicon interconnect technology in FPGA system is introduced, which needs to be accurately modelled over high frequency by considering numerous design requirements. The stacked silicon interposer includes a lot of TSVs for high speed signals. Designs without the consideration of high frequency effects of TSV will degrade the rise/fall time of a signal, increase crosstalk and noise injection, and cause significant performance degradation on high speed channels. The routing metal loss in Under Bump Metallurgy (UBM) layer is also analyzed and simulated. Performance enhancement by using SOI wafer is shown and compared against conventional wafers.