Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS

Three-dimensional (3D) memory stacking is one of the most promising applications in 3D integration to solve the limited memory bandwidth problem in 2D integrated circuits (ICs). However, the high power density, i.e., power dissipation per unit volume, due to the high integration density of 3D ICs may incur high operating temperature and, thus, causes low reliability as well as high power consumption. In this paper, we describes the effects of temperature, supply voltage, and L2 cache access rate on both power consumption and reliability of 3D-stacked L2 DRAM cache. Also, we propose a dynamic voltage and frequency scaling (DVFS) scheme for 3D-stacked L2 DRAM cache which can be adapted to either each cache bank or each group of cache banks while taking account of both error-rate and temperature-induced power consumption. Experimental results show that the proposed DVFS scheme achieved a reduction of energy consumption by up to 21.5% compared to a conventional scheme under a given error-rate constraint.