FPGA implementation of stereoscopic image proceesing architecture base on the gray-scale projection

With the advance of image processing and computer vision, a stereo vision system with two cameras has become the research of interest in many areas since its ability to depth information similar to human vision. Depth map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. In this paper, by analyzing digital image stabilization algorithms, we propose an efficient stereoscopic image architecture which combined gray - scaled projection with Affine transformation model. We develop the architecture by describing the various computation units in hardware description language (Verliog) and synthesizing the design into a FPGA. The synthesis and experimental results show that the proposed architecture is better than traditional SAD(sum of absolute difference) based block matching algorithm in frame rate(frame/sec).