DocumentCode :
589471
Title :
Current equalization scheme for parallel low-dropout regulators
Author :
Katare, Siddharth ; Natarajan, Narayanan
Author_Institution :
MDG-India, Intel Technol. India, Bangalore, India
fYear :
2012
fDate :
4-7 Nov. 2012
Firstpage :
88
Lastpage :
91
Abstract :
Parallel connected low-dropout regulators are used to share the current delivered to a large power plane. Current sharing helps supply large load currents while still using individual low capacity regulators that can be optimized for other attributes such as PSRR and transient response. However, in presence of mismatch in the LDOs, the performance of current sharing degrades significantly. The idea proposed in this paper addresses the load current equalization aspect of parallel connected LDOs in the presence of large within-die variations.
Keywords :
equalisers; power electronics; transient response; LDO; PSRR; current equalization scheme; parallel connected low-dropout regulators; transient response; Feedback loop; Load modeling; Regulators; Semiconductor device modeling; Simulation; Transistors; Voltage control; Low dropout regulators; current sharing LDO; parallel LDO;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
Type :
conf
DOI :
10.1109/ISOCC.2012.6407046
Filename :
6407046
Link To Document :
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