• DocumentCode
    589484
  • Title

    Integration of dual channel timing formatter system for high speed memory test equipment

  • Author

    Jaeseok Park ; Ingeol Lee ; Young-Seok Park ; Sung-Geun Kim ; Kyung Ho Ryu ; Dong-Hoon Jung ; Kangwook Jo ; Choong Keun Lee ; Hongil Yoon ; Seong-Ook Jung ; Woo-Young Choi ; Sungho Kang

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
  • fYear
    2012
  • fDate
    4-7 Nov. 2012
  • Firstpage
    185
  • Lastpage
    187
  • Abstract
    This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.
  • Keywords
    automatic test equipment; integrated memory circuits; timing circuits; dual channel timing formatter system; high speed memory test equipment; timing generator; timing resolution; Calibration; Clocks; Delay; Generators; Image edge detection; Test equipment; ATE; memory test; timing formatter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2012 International
  • Conference_Location
    Jeju Island
  • Print_ISBN
    978-1-4673-2989-7
  • Electronic_ISBN
    978-1-4673-2988-0
  • Type

    conf

  • DOI
    10.1109/ISOCC.2012.6407070
  • Filename
    6407070
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=589484