Error Injection & Correction: An efficient formal logic restructuring algorithm

Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both logic restructuring techniques used in the synthesis and optimization of logic designs. However, not every irredundant target wire can be successfully removed due to some limitations in these two approaches. Therefore, this paper proposes an efficient restructuring technique, Error Injection & Correction (EIC), which formally constructs a corresponding rectification network at feasible locations without verification efforts for the injected errors of the wire removal, addition, or gate replacement. We use the EIC to serve as a logic perturbation engine and combine other logic optimization engines to optimize the circuit. The experimental results show that the size of highly optimized circuits can be further reduced with this EIC technique as compared with the configuration using only logic optimization engines.