Title :
Design of low-power high-radix switch fabric with partially-activated input and output lines
Author :
Jihyun Ryoo ; Seuk Son ; Jaeha Kim
Author_Institution :
Sch. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
A low-power radix-64 switch fabric that achieves more than 10× reduction in power compared to a basic matrix-type implementation is presented. Such a dramatic reduction in power is enabled by partially activating the high-capacitance input and output lines and therefore keeping the switched capacitance small when propagating the signals. For instance, each of the input line is divided by 8 repeaters. Also, each output line is divided into 16 sub-sections, each of which can be routed to the final output port via a hierarchical 16:1 output multiplexer. Based on the transistor-level simulations taking the wire loading into account via detailed floorplanning, the switch core implemented in 45nm CMOS is estimated to have 25-FO4 latency while dissipating only 81-mW.
Keywords :
CMOS logic circuits; circuit layout; logic design; low-power electronics; CMOS; floorplanning; hierarchical 16:1 output multiplexer; low-power high-radix-64 switch fabric design; low-power radix-64 switch fabric; partially-activated input line; partially-activated output line; power 81 mW; power reduction; size 45 nm; switch core; transistor-level simulation; wire loading; hierarchical output multiplexing; high-radix switch fabric core; network-on-chips; serial input multiplexing;
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
DOI :
10.1109/ISOCC.2012.6407081
